The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Aug. 28, 2001
Ali Muhtaroglu, Hillsboro, OR (US);
Ali Muhtaroglu, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for 'input low voltage' (VIL) and 'input high voltage' (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.