The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2006

Filed:

May. 17, 2004
Applicants:

Charles P. Roth, Austin, TX (US);

Ravi P. Singh, Austin, TX (US);

Gregory A. Overkamp, Austin, TX (US);

Thomas Tomazin, Austin, TX (US);

Inventors:

Charles P. Roth, Austin, TX (US);

Ravi P. Singh, Austin, TX (US);

Gregory A. Overkamp, Austin, TX (US);

Thomas Tomazin, Austin, TX (US);

Assignees:

Intel Corporation, Santa Clara, CA (US);

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.


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