The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Aug. 30, 2001
Hiroyuki Takahashi, Kanagawa, JP;
Yoshiyuki Katou, Kanagawa, JP;
Hideo Inaba, Kanagawa, JP;
Shouzou Uchida, Kanagawa, JP;
Masatoshi Sonoda, Kanagawa, JP;
Hiroyuki Takahashi, Kanagawa, JP;
Yoshiyuki Katou, Kanagawa, JP;
Hideo Inaba, Kanagawa, JP;
Shouzou Uchida, Kanagawa, JP;
Masatoshi Sonoda, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell arrayThen, a test signal TEis set '1' to set a device in a test mode. Refresh addresses for test are then stored in a data store circuitA first address for test is applied to an address terminalwhereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell arrayare checked to decide the presence or absence of any abnormality.