The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Jun. 04, 2003
Jawahar Jain, Santa Clara, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Amit Narayan, Redwood City, CA (US);
Debashis Sahoo, Stanford, CA (US);
Christian Stangier, Los Altos, CA (US);
Jawahar Jain, Santa Clara, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Amit Narayan, Redwood City, CA (US);
Debashis Sahoo, Stanford, CA (US);
Christian Stangier, Los Altos, CA (US);
Fujitsu Limited, Kawasaki, JP;
Abstract
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.