The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Mar. 10, 2004
Ramachandra Divakaruni, Ossining, NY (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Oh-jung Kwon, Hopewell Junction, NY (US);
Rajeev Malik, Pleasantville, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Oh-Jung Kwon, Hopewell Junction, NY (US);
Rajeev Malik, Pleasantville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.