The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
May. 23, 2003
Jawahar Jain, Santa Clara, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Amit Narayan, Redwood City, CA (US);
Debashis Sahoo, Stanford, CA (US);
Christian Stangier, Los Altos, CA (US);
Jawahar Jain, Santa Clara, CA (US);
Subramanian K. Iyer, Austin, TX (US);
Amit Narayan, Redwood City, CA (US);
Debashis Sahoo, Stanford, CA (US);
Christian Stangier, Los Altos, CA (US);
Fujitsu Limited, Kawasaki, JP;
Abstract
In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.