The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Jul. 11, 2003
James W. Cady, Austin, TX (US);
Julian Partridge, Austin, TX (US);
James Douglas Wehrly, Jr., Austin, TX (US);
James Wilder, Austin, TX (US);
David L. Roper, Austin, TX (US);
Jeff Buchle, Austin, TX (US);
James W. Cady, Austin, TX (US);
Julian Partridge, Austin, TX (US);
James Douglas Wehrly, Jr., Austin, TX (US);
James Wilder, Austin, TX (US);
David L. Roper, Austin, TX (US);
Jeff Buchle, Austin, TX (US);
Staktek Group L.P., Austin, TX (US);
Abstract
The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.