The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Jun. 11, 2003
Matthew A. Purdy, Austin, TX (US);
Matthew A. Purdy, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
The present invention is generally directed to various methods of controlling optical properties of a capping insulating layer on memory devices, and system for performing same. The method includes forming a first capping layer that includes at least one process layer above a memory cell formed above a first semiconducting substrate, measuring at least one optical characteristic of the first capping layer and determining at least one parameter of a deposition process to form a second capping layer that includes at least one process layer above a memory cell formed above a second semiconducting substrate based upon the measured optical characteristic of the first capping layer. In another case, the method includes performing a deposition process in a deposition tool to form a capping layer that includes at least one process layer above a memory cell on a first substrate, measuring at least one optical characteristic of the capping layer formed above the first substrate, adjusting at least one parameter of the deposition process based upon the measured optical characteristic of the capping layer formed above the first substrate, and performing the deposition process that includes the adjusted parameter in the deposition tool to form a capping layer that includes at least one process layer above a memory cell on a second substrate.