The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Sep. 29, 2003
Jeffrey A. Hall, San Jose, CA (US);
Aritharan Thurairajaratnam, San Jose, CA (US);
Jeffrey A. Hall, San Jose, CA (US);
Aritharan Thurairajaratnam, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.