The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Jun. 17, 2002
Keng L. Wong, Portland, OR (US);
Chee How Lim, Hillsboro, OR (US);
Keng L. Wong, Portland, OR (US);
Chee How Lim, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.