The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Mar. 07, 2005
Applicants:

Michael J. Berman, West Linn, OR (US);

George E. Bailey, Welches, OR (US);

Inventors:

Michael J. Berman, West Linn, OR (US);

George E. Bailey, Welches, OR (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03B 27/32 (2006.01); G03B 27/42 (2006.01); G03B 27/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.


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