The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7022554 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 04, 2006

Filed:

Nov. 13, 2003
Applicants:

Kazuo Kasue, Kyoto, JP;

Takehisa Kajikawa, Nishinomiya, JP;

Satoru Hachinohe, Yokaichi, JP;

Inventors:

Kazuo Kasue, Kyoto, JP;

Takehisa Kajikawa, Nishinomiya, JP;

Satoru Hachinohe, Yokaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a circuit module includes a step of filling the gap between a chip component and a substrate on which the chip component is mounted in a flip chip configuration with resin. The method uses simplified equipment and minimizes the undesired spread of resin. The resin is supplied between the sidewall of a dispenser needle and the sidewall of the chip component. Due to capillary action, a resin pool is formed and then the gap between the chip component and the substrate is spontaneously filled with the resin of the resin pool.


Find Patent Forward Citations

Kasue, Kazuo. (2006). Method for fabricating circuit module (U.S. Patent No. 7022554). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7022554

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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