The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Feb. 03, 2003
Minoru Ogawa, Gifu, JP;
Masahiro Izumi, Gifu, JP;
Shigeyasu Itoh, Gifu, JP;
Shingetsu Yamada, Nagahama, JP;
Shuuji Suzuki, Nagahama, JP;
Hiroo Kurosaki, Nagahama, JP;
Minoru Ogawa, Gifu, JP;
Masahiro Izumi, Gifu, JP;
Shigeyasu Itoh, Gifu, JP;
Shingetsu Yamada, Nagahama, JP;
Shuuji Suzuki, Nagahama, JP;
Hiroo Kurosaki, Nagahama, JP;
Sony Corporation, Tokyo, JP;
Mitsubishi Plastics, Inc., Tokyo, JP;
Abstract
The present invention provides a semiconductor device integrated multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, thereby enabling the production of high density, ultra small three dimensional mounting modules and the like, can also be ideally applied to low volume high mix manufacturing configurations, and has little impact on the environment, and also provides a method of manufacturing such a semiconductor device integrated multilayer wiring board. In the semiconductor device integrated multilayer wiring board, a wiring substrate is formed by embedding conductive wiring within an insulating substrate, formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as primary constituents, so that the surface of the wiring protrudes to the surface of the resin, and a plurality of these wiring substrates are laminated together, IC chips are mounted onto some of the wiring substrates, the insulating substrates of the wiring substrates are bonded together by thermal fusion, and the conductive wiring of each of the wiring substrates, and the wiring electrically connecting the wiring substrates together, is formed from a conductive material produced by curing a conductive paste.