The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2006

Filed:

May. 30, 2000
Applicants:

Hong Wang, Fremont, CA (US);

Ralph Kling, Sunnyvale, CA (US);

Yong-fong Lee, San Jose, CA (US);

David A. Berson, Marietta, GA (US);

Michael A. Kozuch, Beaverton, OR (US);

Konrad Lai, Vancouver, WA (US);

Inventors:

Hong Wang, Fremont, CA (US);

Ralph Kling, Sunnyvale, CA (US);

Yong-Fong Lee, San Jose, CA (US);

David A. Berson, Marietta, GA (US);

Michael A. Kozuch, Beaverton, OR (US);

Konrad Lai, Vancouver, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.


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