The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Sep. 26, 2001
Partha P. Datta Ray, Saratoga, CA (US);
Mikhail I. Grinchuk, Mountainview, CA (US);
Pedja Raspopovic, Raleigh, NC (US);
Partha P. Datta Ray, Saratoga, CA (US);
Mikhail I. Grinchuk, Mountainview, CA (US);
Pedja Raspopovic, Raleigh, NC (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An optimization apparatus and method optimizes a functional block within a netlist of an integrated circuit design. A corresponding delay value is assigned to each of a plurality of pins of the block. Each pin corresponds to a respective signal path through the block. The delay values together form a delay value combination, which is selected from a continuous set of possible combinations in which each combination in the set satisfies a predetermined criteria. A circuit configuration for the block is then generated with a plurality of logic cells that are interconnected in the netlist such that the respective signal paths have delays through the block that are based on the corresponding delay values.