The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Nov. 12, 2004
Tsung-min Hsieh, Miaoli, TW;
Jhyy-cheng Liou, Jhubei, TW;
Chien-hsing Lee, Jhubei, TW;
Chin-hsi Lin, Hsinchu, TW;
Tsung-Min Hsieh, Miaoli, TW;
Jhyy-Cheng Liou, Jhubei, TW;
Chien-Hsing Lee, Jhubei, TW;
Chin-Hsi Lin, Hsinchu, TW;
Solid State System Co., Ltd., Hsinchu, TW;
Abstract
A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.