The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7018893 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 28, 2006

Filed:

Dec. 15, 2004
Applicant:

Srivatsa Kundalgurki, Dresden, DE;

Inventor:

Srivatsa Kundalgurki, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

Bottom electrodes of stacked capacitor cells are formed by lining a patterned hard mask with a conductive layer. The hard mask is formed by a layered stack. Subsequent to the formation of trenches within the hard mask, the top-most masking layer of the layer stack is laterally recessed. The bottom electrode layer is then deposited to line the trenches. Following this, the bottom electrode layer is removed from the top of the hardmask. Subsequently, the hard mask is removed. As a result, released and free-standing elements of the conductive layer are formed as bottom electrodes that include a hydrophobic contact area in the top part of the bottom electrodes.


Find Patent Forward Citations

Kundalgurki, Srivatsa. (2006). Method for fabricating bottom electrodes of stacked capacitor memory cells (U.S. Patent No. 7018893). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7018893

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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