The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Dec. 22, 2003
Pinghai Hao, Plano, TX (US);
Larry B. Anderson, Santa Cruz, CA (US);
Fan Chi Hou, McKinney, TX (US);
Xiaoju Wu, Irving, TX (US);
Yvonne Patton, Plano, TX (US);
Shanjen Pan, Plano, TX (US);
Zafar Imam, Dallas, TX (US);
Pinghai Hao, Plano, TX (US);
Larry B. Anderson, Santa Cruz, CA (US);
Fan Chi Hou, McKinney, TX (US);
Xiaoju Wu, Irving, TX (US);
Yvonne Patton, Plano, TX (US);
Shanjen Pan, Plano, TX (US);
Zafar Imam, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (). The method comprises forming an oxide layer () on a silicon substrate () and depositing a polysilicon layer () on the oxide layer (). The method further includes implanting a fluorine dopant () into the polysilicon layer () at an implant dose of at least about 4×10atoms/cm. The polysilicon layer () is thermally annealed such that a portion of the fluorine dopant () is diffused into the oxide layer () to thereby reduce a 1/f noise of the MOS device (). Other embodiments of the provide a MOS device () manufactured by the above-described method and a method of manufacturing an integrated circuit () that includes the above-described method.