Synchronous flash memory with virtual segment architecture

Abstract

An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.