The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2006

Filed:

Oct. 05, 2004
Applicants:

Tsuneo Kawamata, Tokyo, JP;

Masatoshi Hasegawa, Tokyo, JP;

Keinosuke Toriyama, Hitachinaka, JP;

Tomofumi Hokari, Tokyo, JP;

Inventors:

Tsuneo Kawamata, Tokyo, JP;

Masatoshi Hasegawa, Tokyo, JP;

Keinosuke Toriyama, Hitachinaka, JP;

Tomofumi Hokari, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.


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