The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7013441 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 14, 2006

Filed:

Sep. 26, 2003
Applicants:

Jeanne P. Bickford, Essex Junction, VT (US);

Edward K. Evans, Essex Junction, VT (US);

Sean Horner, Burlington, VT (US);

Raymond J. Rosner, Colchester, VT (US);

Andrew Wienick, South Burlington, VT (US);

Joseph Yoder, Oakton, VA (US);

Inventors:

Jeanne P. Bickford, Essex Junction, VT (US);

Edward K. Evans, Essex Junction, VT (US);

Sean Horner, Burlington, VT (US);

Raymond J. Rosner, Colchester, VT (US);

Andrew Wienick, South Burlington, VT (US);

Joseph Yoder, Oakton, VA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.


Find Patent Forward Citations

Bickford, Jeanne. (2006). Method for modeling integrated circuit yield (U.S. Patent No. 7013441). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7013441

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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