The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2006
Filed:
Feb. 12, 2004
Shin Su, Hsinchu, TW;
Chun-hsiang Lai, Hsinchu, TW;
Chia-ling LU, Hsinchu, TW;
Yen-hung Yeh, Hsinchu, TW;
Tao-cheng LU, Hsinchu, TW;
Shin Su, Hsinchu, TW;
Chun-Hsiang Lai, Hsinchu, TW;
Chia-Ling Lu, Hsinchu, TW;
Yen-Hung Yeh, Hsinchu, TW;
Tao-Cheng Lu, Hsinchu, TW;
MACRONIX International Co., Ltd., Hsinchu, TW;
Abstract
An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.