The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2006
Filed:
Jan. 09, 2003
Ming-ta Lei, Hsin-Chu, TW;
Yih-shung Lin, Sanchung, TW;
Ai-sen Liu, Hsin-Chu, TW;
Cheng-chung Lin, Taipei, TW;
Baw-ching Perng, Hsin-Chu, TW;
Chia-hui Lin, Hsin-Chu, TW;
Ming-Ta Lei, Hsin-Chu, TW;
Yih-Shung Lin, Sanchung, TW;
Ai-Sen Liu, Hsin-Chu, TW;
Cheng-Chung Lin, Taipei, TW;
Baw-Ching Perng, Hsin-Chu, TW;
Chia-Hui Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin Chu, TW;
Abstract
A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.