The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Aug. 01, 2001
Shauki Elassaad, Los Altos, CA (US);
Alexander Saldanha, El Cerrito, CA (US);
Shauki Elassaad, Los Altos, CA (US);
Alexander Saldanha, El Cerrito, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile