The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2006

Filed:

Jul. 22, 2002
Applicants:

Boon Tang Teh, Penang, MY;

Edward V. Bautista, Jr., Santa Clara, CA (US);

Ken Cheong Cheah, Penang, MY;

Colin Bill, Cupertino, CA (US);

Joseph Kucera, Austin, TX (US);

Weng Fook Lee, Penang, MY;

Darlene G. Hamilton, San Jose, CA (US);

Inventors:

Boon Tang Teh, Penang, MY;

Edward V. Bautista, Jr., Santa Clara, CA (US);

Ken Cheong Cheah, Penang, MY;

Colin Bill, Cupertino, CA (US);

Joseph Kucera, Austin, TX (US);

Weng Fook Lee, Penang, MY;

Darlene G. Hamilton, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.


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