The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2006

Filed:

May. 28, 2003
Applicants:

Fulong Zhang, Willow Grove, PA (US);

William B. Andrews, Allentown, PA (US);

Phillip Johnson, Allentown, PA (US);

Hal Scholz, Allentown, PA (US);

Zheng (Jeff) Chen, Allentown, PA (US);

John Schadt, Allentown, PA (US);

Inventors:

Fulong Zhang, Willow Grove, PA (US);

William B. Andrews, Allentown, PA (US);

Phillip Johnson, Allentown, PA (US);

Hal Scholz, Allentown, PA (US);

Zheng (Jeff) Chen, Allentown, PA (US);

John Schadt, Allentown, PA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.


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