The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2006

Filed:

Jan. 28, 2003
Applicants:

Shi-tron Lin, Taipei, TW;

Wei-fan Chen, Taichung, TW;

Chenhsin Lien, Hsinchu, TW;

Inventors:

Shi-Tron Lin, Taipei, TW;

Wei-Fan Chen, Taichung, TW;

Chenhsin Lien, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 26/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.


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