The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
May. 06, 2004
James W. Adkisson, Jericho, VT (US);
Gary B. Bronner, Stormville, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Ramachandra Divakaruni, Ossining, NY (US);
Carl J. Radens, LaGrangeville, NY (US);
James W. Adkisson, Jericho, VT (US);
Gary B. Bronner, Stormville, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Ramachandra Divakaruni, Ossining, NY (US);
Carl J. Radens, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.