The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Aug. 06, 2003
Bong-hyun Kim, Incheon, KR;
Hun-hyeoung Lim, Gyeonggi-do, KR;
Hyeon-deok Lee, Seoul, KR;
Yong-woo Hyung, Gyeonggi-do, KR;
Bong-Hyun Kim, Incheon, KR;
Hun-Hyeoung Lim, Gyeonggi-do, KR;
Hyeon-Deok Lee, Seoul, KR;
Yong-Woo Hyung, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.