The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Jun. 18, 2002
Mitsuya Kinoshita, Hyogo, JP;
Tetsushi Tanizaki, Hyogo, JP;
Masaru Haraguchi, Hyogo, JP;
Katsumi Dosaka, Hyogo, JP;
Mitsuya Kinoshita, Hyogo, JP;
Tetsushi Tanizaki, Hyogo, JP;
Masaru Haraguchi, Hyogo, JP;
Katsumi Dosaka, Hyogo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.