The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Dec. 25, 2002
Hiroyuki Takahashi, Kanagawa, JP;
Takuya Hirota, Kanagawa, JP;
Noriaki Komatsu, Kanagawa, JP;
Atsushi Nakagawa, Kanagawa, JP;
Susumu Takano, Kanagawa, JP;
Masahiro Yoshida, Kanagawa, JP;
Yuuji Torige, Kanagawa, JP;
Hideo Inaba, Kanagawa, JP;
Hiroyuki Takahashi, Kanagawa, JP;
Takuya Hirota, Kanagawa, JP;
Noriaki Komatsu, Kanagawa, JP;
Atsushi Nakagawa, Kanagawa, JP;
Susumu Takano, Kanagawa, JP;
Masahiro Yoshida, Kanagawa, JP;
Yuuji Torige, Kanagawa, JP;
Hideo Inaba, Kanagawa, JP;
NEC Electronics Corp., Kanagawa, JP;
Abstract
Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/Fis set by a one shot pulse from an OS circuit, a memory access request is inputted to a memory accessing pulse generator circuitthrough a NOR gate, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gateduring the memory access, the output of the NOR gateis at the 'L' level, and the refresh request is blocked by the AND gate. Thereafter, at the time when the latch control signal LC is turned into the 'L' level, F/Fsandare reset, the output of the NOR gateis turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit, and a refresh enable signal RERF is outputted.