The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2006

Filed:

Jun. 07, 2004
Applicants:

Todd A. Merritt, Boise, ID (US);

Timothy B. Cowles, Boise, ID (US);

Vikram K. Bollu, Boise, ID (US);

Inventors:

Todd A. Merritt, Boise, ID (US);

Timothy B. Cowles, Boise, ID (US);

Vikram K. Bollu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method using a reduced number of fuses for enabling redundant memory blocks in a semiconductor memory is disclosed. In one embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse selects a pair of repair modules. In another embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse may select a power of two (i.e., 1, 2, 4, 8, etc.) number of repair modules. Each repair module includes fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the Least Significant Bit (LSB) is uninvolved in the address programming. Instead, the LSB is compared to the values of the selection fuses. As a result, repair modules select a redundant memory block based on a combination of the selected address comparison and the separate LSB comparison.


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