The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Feb. 20, 2004
Nao Miyamoto, Yokohama, JP;
Toshiyuki Sakuta, Hamura, JP;
Nao Miyamoto, Yokohama, JP;
Toshiyuki Sakuta, Hamura, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one. A signal transferring path includes a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits for acquiring and holding signals by use of clock signals. The signal transferring path includes a first and a second signal transferring path. The first signal transferring path is constituted by enhancement-type MOSFETs and has a signal transferring delay time equal to, or less than, a permissible signal transferring delay time. The second signal transferring path is configured such that, among the above-mentioned plurality of logic gate circuits, a logic gate circuit having a delay time longer than the above-mentioned permissible signal transferring delay time when constituted using enhancement-type MOSFETs is replaced with a depletion-type MOSFET so that the second signal transferring path may provide a signal transferring delay time equal to or less than the permissible signal transferring delay time mentioned above.