The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Dec. 31, 2002
Llyoung Kim, Plainsboro, NJ (US);
Laurence Reeves, Crowthorne, GB;
Paul W. Rutkowski, Bridgewater, NJ (US);
Jing Wu, North Brunswick, NJ (US);
Llyoung Kim, Plainsboro, NJ (US);
Laurence Reeves, Crowthorne, GB;
Paul W. Rutkowski, Bridgewater, NJ (US);
Jing Wu, North Brunswick, NJ (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.