The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
May. 24, 2004
Hiu Fung Ip, San Jose, CA (US);
Ellick MA, San Jose, CA (US);
Yan Ling Yu, Shanghai, CN;
Ren Chong, Shanghia, CN;
Ji-wei Sun, Shanghai, CN;
Hiu Fung Ip, San Jose, CA (US);
Ellick Ma, San Jose, CA (US);
Yan Ling Yu, Shanghai, CN;
Ren Chong, Shanghia, CN;
Ji-Wei Sun, Shanghai, CN;
BCD Semiconductor Manufacturing Ltd., Hamilton, BM;
Abstract
A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.