Hierarchical general interconnect architecture for high density fpga's

Abstract

Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a hierarchical general interconnect architecture in which: (1) reliance on single-length general interconnect lines is avoided; (2) the next greater length of general interconnect line is at least double-reach length (triple span); and (3) yet greater lengths of general interconnect line (e.g., Deca-Reach Length, or 11-span) can feed signals into logic blocks indirectly through switching resources of the shorter length, general interconnect line rather than feeding such signals directly into the logic blocks through their own respective switching resources. Additionally, the yet greater lengths of general interconnect line (e.g., Deca-Reach Length) have a fewer number of signal tap points on them than the number of logic blocks spanned by such longer ones of the general interconnect lines. Navigation limiting rules may be established to reduce the number of drive buffers needed for driving signals onto the longer ones of the general interconnect lines. In one embodiment, there are no drive buffers for middle tap points of the longer ones of the general interconnect lines.