The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2006
Filed:
May. 31, 2001
Richard P. Mackey, Phoenix, AZ (US);
Richard P. Luckett, Phoenix, AZ (US);
James D. Warren, Chandler, AZ (US);
Sailesh Bissessur, Gilbert, AZ (US);
Richard P. Mackey, Phoenix, AZ (US);
Richard P. Luckett, Phoenix, AZ (US);
James D. Warren, Chandler, AZ (US);
Sailesh Bissessur, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.