The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Sep. 14, 1999
Taizo Yamawaki, Tokyo, JP;
Takefumi Endo, Takasaki, JP;
Kazuo Watanabe, Takasaki, JP;
Kazuaki Hori, Yokohama, JP;
Julian Hildersley, Orwell, GB;
Taizo Yamawaki, Tokyo, JP;
Takefumi Endo, Takasaki, JP;
Kazuo Watanabe, Takasaki, JP;
Kazuaki Hori, Yokohama, JP;
Julian Hildersley, Orwell, GB;
Renesas Technology Corp., Tokyo, JP;
TTPCom.Limited, Melbourn, GB;
Abstract
In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.