The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Jun. 14, 2004
Randy J. Schwindt, Portland, OR (US);
Randy J. Schwindt, Portland, OR (US);
Cascade Microtech, Inc., Beaverton, OR (US);
Abstract
A low-current probe card for measuring currents down to the femtoamp region includes a dielectric board, such as of glass-epoxy material, forming an opening. A plurality of probing devices, such as ceramic blades, are edge-mounted about the opening so that the probing elements or needles included thereon terminate below the opening in a pattern suitable for probing a test device. A plurality of cables are attached to the card for respectively connecting each device to a corresponding channel of a test instrument. The on-board portion of each cable is of coaxial type and includes an inner layer between the inner dielectric and outer conductor for suppressing the triboelectric effect. An inner conductive area and a conductive backplane that are respectively located below and on one side of each device are set to guard potential via the outer conductor of the corresponding cable so as to guard the signal path on the other side of the device. The lead-in portion of each cable, which is detachably connected to the corresponding on-board portion through a plug-in type connector, is of triaxial type and includes, besides the inner layer between the inner dielectric and outer conductor, a second inner dielectric and second outer conductor. A conductive cover and an outer conductive area that substantially enclose the components on the card are set to shield potential via the second outer conductor and connector.