The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Dec. 09, 2003
Wolfgang Siebert, Mehring, DE;
Peter Storck, Mehring, DE;
Wolfgang Siebert, Mehring, DE;
Peter Storck, Mehring, DE;
Siltronic AG, Munich, DE;
Abstract
A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface, wherein the surface of the epitaxial layer has a maximum density of 0.14 localized light scatterers per cmwith a cross section of greater than or equal to 0.12 μm, and the front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 μm×1 μm reference area. There is also a process for producing a semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. The process includes the following: (a) a stock removal polishing step as the only polishing step; (b) cleaning and drying of the semiconductor wafer; (c) pretreatment of the front surface of the semiconductor wafer at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor; and (d) deposition of the epitaxial layer on the front surface of the pretreated semiconductor wafer.