The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Jul. 28, 2003
Hieu Van Tran, San Jose, CA (US);
Sakhawat M. Khan, Los Altos, CA (US);
William John Saiki, Mountain View, CA (US);
George J. Korsh, Redwood City, CA (US);
Hieu Van Tran, San Jose, CA (US);
Sakhawat M. Khan, Los Altos, CA (US);
William John Saiki, Mountain View, CA (US);
George J. Korsh, Redwood City, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.