The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Apr. 28, 2004
Panayotis C. Andricacos, Croton-on-Hudson, NY (US);
Tien-jen J. Cheng, Bedford, NY (US);
Emanuel I. Cooper, Scarsdale, NY (US);
David E. Eichstadt, Park Ridge, IL (US);
Jonathan H. Griffith, Lagrangeville, NY (US);
Randolph F. Knarr, Goldens Bridge, NY (US);
Roger A. Quon, Rhinebeck, NY (US);
Erik J. Roggeman, Fishkill, NY (US);
Panayotis C. Andricacos, Croton-on-Hudson, NY (US);
Tien-Jen J. Cheng, Bedford, NY (US);
Emanuel I. Cooper, Scarsdale, NY (US);
David E. Eichstadt, Park Ridge, IL (US);
Jonathan H. Griffith, Lagrangeville, NY (US);
Randolph F. Knarr, Goldens Bridge, NY (US);
Roger A. Quon, Rhinebeck, NY (US);
Erik J. Roggeman, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.