The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2006

Filed:

Dec. 29, 2000
Applicants:

Leslie E. Cline, Sunnyvale, CA (US);

Xia Dai, San Jose, CA (US);

Varghese George, Folsom, CA (US);

Robert L. Farrell, Gold River, CA (US);

Inventors:

Leslie E. Cline, Sunnyvale, CA (US);

Xia Dai, San Jose, CA (US);

Varghese George, Folsom, CA (US);

Robert L. Farrell, Gold River, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.


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