The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2006

Filed:

Dec. 06, 2004
Applicants:

Jong Sik Paek, Seoul, KR;

IN Bae Park, Seoul, KR;

Seong Min Seo, Seoul, KR;

Inventors:

Jong Sik Paek, Seoul, KR;

In Bae Park, Seoul, KR;

Seong Min Seo, Seoul, KR;

Assignee:

Amkor Technology, Inc., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.


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