The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2006
Filed:
Mar. 05, 2003
Ramkumar Subramanian, Sunnyvale, CA (US);
Bharath Rangarajan, Santa Clara, CA (US);
Catherine B. Labelle, San Jose, CA (US);
Bhanwar Singh, Morgan Hill, CA (US);
Christopher F. Lyons, Fremont, CA (US);
Ramkumar Subramanian, Sunnyvale, CA (US);
Bharath Rangarajan, Santa Clara, CA (US);
Catherine B. Labelle, San Jose, CA (US);
Bhanwar Singh, Morgan Hill, CA (US);
Christopher F. Lyons, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.