Method for analyzing path delays in an ic clock tree

Abstract

A macro-cell is incorporated into an integrated circuit (IC) design to describe a fixed arrangement of cells to be included in the IC. The IC includes a clock tree for delivering a clock signal from its root to all clocked devices (sinks) within the IC external to the macro-cell, and to a root of a clock tree subtree included within the macro-cell for delivering the clock signal from its root to sinks residing within the macro-cell. A model of the subtree depicts the maximum and minimum delays of the clock signal's rising and falling edges between the subtree root and the sinks within the macro-cell as functions of the clock signal's rising and falling edge transition times as they arrives at the subtree root and also as functions of the relative amount of delay the rising and falling edges experience as they pass from the clock tree root to the subtree root. A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signal's rising and falling edges as they pass from the clock tree root to any sink of the IC.