The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Jul. 30, 2002
Shen Lin, Foster City, CA (US);
Norman Chang, Fremont, CA (US);
Weize Xie, Cupertino, CA (US);
Richard Chou, Cupertino, CA (US);
Shen Lin, Foster City, CA (US);
Norman Chang, Fremont, CA (US);
Weize Xie, Cupertino, CA (US);
Richard Chou, Cupertino, CA (US);
Apache Design Solutions, Inc., Palo Alto, CA (US);
Abstract
An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.