The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2005

Filed:

Dec. 21, 1998
Applicants:

Mark I. Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Austin, TX (US);

Derick J. Wristers, Austin, TX (US);

Inventors:

Mark I. Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Austin, TX (US);

Derick J. Wristers, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/36 ;
U.S. Cl.
CPC ...
Abstract

A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.


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