The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Oct. 01, 2003
Applicants:
Jau-wen Chen, Cupertino, CA (US);
Yoon Huh, San Jose, CA (US);
Peter Bendix, Redwood City, CA (US);
Inventors:
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/62 ;
U.S. Cl.
CPC ...
Abstract
A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
Chen, Jau-Wen. (2005). Substrate-biased i/o and power esd protection circuits in deep-submicron twin-well process (U.S. Patent No. 6979869). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6979869
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile