The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Jan. 23, 2004
Kazunari Hatade, Tokyo, JP;
Kazunari Hatade, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (), a p-type impurity region () is formed between an NMOS () and a PMOS () and in contact with a p-type well (). An electrode () resides on the p-type impurity region () and the electrode () is connected to a high-voltage-side floating offset voltage (VS). The p-type impurity region () has a higher impurity concentration than the p-type well () and is shallower than the p-type well (). Between the p-type impurity region () and the PMOS (), an n-type impurity region () is formed in the upper surface of the n-type impurity region (). An electrode () resides on the n-type impurity region () and the electrode () is connected to a high-voltage-side floating supply absolute voltage (VB).